The following are the prior art for performing A/D conversion in columns of a CMOS image sensor.    [1] U.S. Pat. No. 2,532,374 Description    [2] A. Simoni, A. Sartori, M. Gottaidi, A. Zorat, “A digital vision sensor”, Sensors and Actuators, A 46-47, pp. 439-443, 1995    [3] T. Sugiki, S. Ohsawa, H. Miura, M. Sasaki, N. Nakamura, I. Inoue, M. Hoshino, Y. Tomizawa, T. Arakawa, “A 60 mW 10b CMOS image sensor with column-to-column FPN reduction”, Dig. Tech. Papers, Int. Solid-State Circuits Conf., pp. 108-109, 2000    [4] B. Mansoorian, H. Y. Yee, S. Huang, E. Fossum, “A 250 mW 60 frames/s 1280×720 pixel 9b CMOS digital image sensor”, Dig. Tech. Papers, Int. Solid-State Circuits Conf., pp. 312-313, 1999    [5] S. Decker, R. D. McGrath, K. Bremer, C. G. Sodini, “A 256×256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output”, IEEE J. Solid-State Circuits, Vol. 33, No. 12, December 1998    [6] K. Nagaraj, “Efficient circuit configuration for algorithmic analog to digital converters”, IEEE Transactions on Circuits and Systems II: Analog and digital signal processing, Vol. 40, NO. 12, pp. 777-785, December 1993
[1] concerns 8-bit integrating A/D converter elements integrated in columns using a lamp signal generator, comparator and register. A similar technology is also reported in [2]. [3] also concerns integrating A/D converter elements in columns, where 10b is implemented using a higher precision comparator. In these integrating A/D converters, the conversion time is long, and in particular increasing the resolution increases the conversion time exponentially, and higher resolution cannot be expected in this status. The advantage, however, is that linearity is good.
[4] reports that operating serial comparison type A/D converters are arrayed in columns and operated using a capacitor, with which high-speed A/D conversion can be possible, so this technology is suitable for an image sensor with a high frame rate and a high number of pixels. The actually accuracy, however, is still about 8-bits. [5] reports on arranging and operating two stages of cyclic type A/D converter elements in columns, which is also suitable for high-speed A/D conversion. However the circuit scale is large since two amplifiers are used. [6] seems to be similar to the present invention, but has a different way of using a capacitor, and is not considered for integrating it.
Beside the above, some image sensors having A/D conversion elements in pixels have been reported, but these are not directly related to the present invention, and are therefore omitted here.
The circuits in [5] of the prior art, which is most closely related to the present invention, will be described. In this prior art, two stages of 1-bit A/D conversion circuits are cascade-connected, and cyclic type A/D conversion is performed by returning the output thereof to input as shown in FIG. 1. In this method, an amplifier is required for each stage, which increases an area and also increases power consumption. If this technology is used as an A/D converter to be integrated in the column of an image sensor, three amplifiers, including an amplifier for noise cancellation and an amplifier for an A/D converter, are required for each column.